1. Field of the Invention
This invention relates to semiconductor fabrication technologies, and more particularly, to a method of fabricating a shallow-trench isolation (STI) structure in integrated circuit that can prevent the STI structure from having microscratches and defects.
2. Description of Related Art
Isolation structures are formed in an integrated circuit for the purpose of preventing carriers from penetrating through the substrate to neighboring components. In a DRAM (dynamic random-access memory) device, for example, the FETs (field effect transistors) are isolated from each other by isolation structures so as to prevent charge leakage among the FETs. Conventionally, an isolation structure is formed by extending thick oxide layers beneath the substrate. One example of this technique is the so-called LOCOS (local oxidation of silicon) technique, which is widely utilized in the semiconductor industry to provide isolation structures among the various components on an IC device. However, the LOCOS technique still has some drawbacks, such as stress and bird's beak problems. The bird's beak problem is particularly undesirable since it can cause the isolation structures to be less effective when the IC device is further downsized for high integration.
One solution to the foregoing problem is to utilize the so-called shallow-trench isolation (STI) structure in place of the LOCOS structure. The method of forming STI structures includes the steps of performing an anisotropic etching process with a mask layer of silicon nitride to form shallow trenches at predefined locations, and then filling these trenches with oxide. One benefit of this method is that the topmost surface of the STI structure can be level with the topmost surface of the substrate.
FIGS. 1 through 5 are schematic, cross-sectional diagrams used to depict the steps involved in a conventional method for fabricating an STI structure in an integrated circuit. FIG. 6 is a schematic top view of the wafer of FIG. 5 (which is a cross-sectional view of FIG. 6 cutting through the line I--I in FIG. 6).
Referring first to FIG. 1, the STI structure is constructed on a semiconductor substrate 10, such as a silicon substrate. An oxide layer 22 is formed over the substrate to serve as a pad oxide layer for surface protection of the substrate 10. After this, a layer of silicon nitride layer 24 is formed over the oxide layer 22 Next, a photoresist layer 28 is formed over the silicon nitride layer 24, which is then selectively removed through a photolithographic and etching process to expose those regions where shallow trenches are to be formed. Subsequently, with the remaining photoresist layer 28 serving as a mask, an etching process is performed on the wafer, whereby those portions of the silicon nitride layer 24, the oxide layer 22, and the substrate 10 that are exposed by the photoresist layer 28 are etched away until reaching a predefined controlled depth in the substrate 10. Through this process, a plurality of shallow trenches 30 is formed in the substrate 10. After this, the entire photoresist layer 28 is removed.
Referring next to FIG. 2, in the subsequent step, a thermal oxidation process is performed on the wafer, whereby a liner oxide layer 31 is formed over the exposed surfaces of the trenches 30. Next, an APCVD (atmospheric-pressure chemical-vapor deposition) process is performed on the wafer, in which TEOS (tetra-ethyl-ortho-silicate) is used as the gas source, to thereby form a TEOS oxide layer 32 to a thickness above the silicon nitride layer 24. Subsequently, the TEOS oxide layer 32 undergoes a densification process at a temperature of about 1,000.degree. C. for a duration of from 10 min. to 30 min. (minutes).
Referring further to FIG. 3, after the densification process, a CMP (chemical-mechanical polish) process is performed on the wafer until the silicon nitride layer 24 is exposed. Through this process, all the part of the TEOS oxide layer 32 that lies above the topmost surface of the silicon nitride layer 24 is removed, leaving only the part that is in the trenches 30. The part of the TEOS oxide layer 32 remaining after the CMP process then serves as TEOS oxide plugs in the trenches 30, which are here designated by the reference numeral 34. One drawback to the CMP process, however, is that it causes microscratches 25 on the TEOS oxide plugs 34 t , which are defects in the STI structure.
Referring further to FIG. 4, in the subsequent step, the silicon nitride layer 24 is entirely removed through an etching process. The etchant can be, for example, hot phosphoric acid.
Referring next to FIG. 5, in the subsequent step, an etching process is performed by submerging the entire wafer in a solution of hydrofluoric acid (HF). The HF solution can etch both the oxide layer 22 and the TEOS oxide plugs 34, but has a faster etching rate on the TEOS oxide plugs 34 than on the oxide layer 22. Therefore, when the oxide layer 22 is entirely etched away, the topmost surface of the remaining part of the TEOS oxide plugs 34 is nearly level with the topmost surface of the substrate 10. However, since the HF solution etches into TEOS oxide plugs 34 at a substantially equal etching rate in all directions, the part of the TEOS oxide plugs 34 remaining after the etching process still has microscratches 35 that are formed due to the existence of the original microscratches 25 shown in FIG. 4. As illustrated in the top view of FIG. 6, these microscratches 35 are scattered over the entire top surface of the TEOS oxide plugs 34 of the resultant STI structure. These microscratches 35 can cause the occurrence of a bridging effect or short-circuit between the circuit components that are intended to be electrically isolated by the STI structure. The yield rate of the IC manufacture is therefore low.